The entire topic of digital circuit timing boils down to one fundamental truth: signals do not travel instantly. Everything else is about managing the consequences of this delay.

The Core Mental Model of Digital Timing

1. Combinational Logic Delays

Every logic gate or wire has a delay. To manage this, we care about two numbers for any path through a circuit:

• Propagation Delay ($t_{pd}$): The maximum time it takes for the output to become stable after an input changes. Think of this as the "worst-case" or longest possible delay for a given path.
• Contamination Delay ($t_{cd}$): The minimum time it takes for the output to start changing after an input changes. This is the "best-case" or shortest possible delay.

In any complex circuit, the overall speed is determined by the Critical Path, which is the path with the longest total propagation delay ($t_{pd}$). The shortest path determines the minimum contamination delay ($t_{cd}$).

2. Sequential Logic Timing (The Two Golden Rules)

In a synchronous (clocked) circuit, logic is placed between registers like D flip-flops. The goal is to ensure that data calculated by the logic is captured correctly by the next register at each clock tick. This gives us two critical rules that you absolutely must know.

Rule 1: The Setup Time Constraint (The "Too Slow" Problem)

Your data must arrive at the next register's input before the clock ticks and be stable for a certain period, known as the setup time ($t_{setup}$). The signal has to travel from the first register, through the slowest logic path (the critical path), and still get to the second register in time.

This leads to the most important equation for determining a circuit's maximum speed:

$$ T_c≥t_{pcq}+t_{pd}(\text{max})+t_{setup} $$

• $T_c$ is the clock period (how fast your clock is).