Pipelining is a method to improve performance by enhancing throughput. Individual instruction has same or even more latency, but the enhanced throughput covers it.

Typically a pipeline without a stall is

$x \text{ instructions}+ (n-1) \text{ cycles per instruction}$

For example, MIPS requires 5 cycles per instruction and if we are running 3 instructions, non-pipelined version will take $5 \times 3 = 15$ cycles to complete the task. On the other hand a pipelined version without considering stall would be $3 + (5-1) = 3 + 4 = 7$ cycles.

This means 2.1428571429 times speedup!

The five cycles/stages needed for MIPS are as follows:

  1. IF: Instruction Fetch (from Instruction Memory)
  2. ID: Instruction Decode and Register Read
  3. EX: Execute operation or calculate address
  4. MEM: Access Memory operand
  5. WB: Write result back to register

image.png

As you can see in the image, we write in the first half and read in the second half. This avoids the structural hazard we will see later.

How does each command differ?

There are lots of commands but for now we only need to remember for three different instruction types:

R-format, lw, sw, beq. While lw, sw, beq are both I format, they differ from what stages to take.